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A 40-Gb/s integrated parallel optical receiver front-end amplifier for VSR (very short reach) optical fiber transmission systems has been developed. It was designed and fabricated in a 0.18-mum CMOS technology and consists of 12 channels in parallel with a data rate of 3.318-Gb/s in each channel. A regulated-cascode (RGC) structure and noise optimization were used in the design of transimpedance amplifier (TIA), which overcomes the inadequate bandwidth problem caused by the large parasitic capacitance effect of the photodiode and CMOS transistors. An isolation structure combined with P+ guard-ring (PGR), N+ guard-ring (NGR), and deep-n-well (DNW) for parallel amplifier is also presented, which could effectively reduce the crosstalk and suppress the substrate noise coupling. The experimental results indicate that, with a parasitic capacitance of 2 pF at the input node, a single channel is able to work at 3.318 Gb/s and a clear eye diagram is obtained with a 2 mVpp input. With a 1.8 V supply, each channel of the front-end amplifier consumes a DC power of 85 mW, and the total power consumption of 12 channels is about 1 W.