Referenced Items are not available for this document.
Test Generation in Systolic Architecture for Multiplication Over 
Test Generation in Systolic Architecture for Multiplication Over
This paper presents a test generation technique for detecting stuck-at (SAF) and transition delay fault (TDF) at gate level in the finite-field systolic multiplier over GF(2m) based on polynomial basis. The proposed technique derives test vectors from the cell expressions of systolic multipliers without any requirement of Automatic test Pattern Generation (ATPG) tool. The complete systolic architecture is C-testable for SAF and TDF with only six constant tests. The test vectors are independent of the multiplier size. The test set provides 100% single SAF and TDF coverage.
Published in:
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
(Volume:18
,
Issue:
9
)
Date of Publication: Sept. 2010
- Page(s):
- 1366 - 1371
- ISSN :
- 1063-8210
- INSPEC Accession Number:
- 11477339
- Digital Object Identifier :
- 10.1109/TVLSI.2009.2023381
- Product Type:
- Journals & Magazines
- Date of Publication :
- 01 September 2009
- Date of Current Version :
- 23 August 2010
- Issue Date :
- Sept. 2010
- Sponsored by :
- IEEE Circuits and Systems Society
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