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Synthesis of VLSI architectures for two-dimensional discrete wavelet transforms

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2 Author(s)
Jongwoo Bae ; Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA ; Prasanna, V.K.

We propose VLSI architectures with parallel I/O capability to compute the Two-Dimensional Discrete Wavelet Transform. Our design can handle large images arriving at high frame rates. A video codec based on our architecture can support multiple channels in parallel and can provide the needed performance for network based video applications. Our architecture with parallel I/O offers a solution for the low power needs of mobile/visual communication systems. Our architecture employs block-based I/O and a dual memory buffer to store intermediate results to schedule the filter operations. This leads to a high throughput rate of n pixels per clock cycle and a small memory size of j(l-1)/(N+n)+2n 2, for an N×N input image, where n×n is the block size, l is the alter length, and j is the number of octaves. The resulting architecture has a latency of 2l+n for each octave and a total execution time of N2/n+2l+n+3jn

Published in:

Application Specific Array Processors, 1995. Proceedings. International Conference on

Date of Conference:

24-26 Jul 1995

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