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In the deep sub-micron domain wires consume more power than transistors. Power Gating for Wires is a form of bus segmentation that alleviates the power loss from on-chip interconnects, by switching off the supply voltage from inactive drivers, cycle by instruction-cycle. The success of Power Gating for Wires depends much on control: the gain from segmentation can conceivably be undone by control costs. Yet during design exploration, the data required for statistical analysis are not available. A theory of efficient control for Power Gating for Wires and a design framework, determining the balance of cost factors, at an early stage, are both needed. In this paper, we formulate a theory of Useful State Analysis to obtain minimal-redundancy encoding of control information. We establish two figures of merit, based on network topology: Intrinsic Sectioning Gain and Useful Encoding Efficiency. They quantify the power loss reduction achievable, and the success of Useful State Analysis in keeping control costs low. We propose a design pattern for the operation of a control plane, wherein the costs of control can be identified. From use cases, we find that architectures can have an Intrinsic Sectioning Gain of 50% and more. Useful Encoding Efficiency is found to be in a range of 44-80% for some common multipath architectures. Although ultimately, the limits of feasibility to control Power Gating for Wires must be decided by means of statistical analysis, we find Useful State Analysis is applicable to networks with tens of terminals, and that our method of control scales well with increasing network size and complexity.