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In this paper, we studied the characteristic of the data acquired by both the combinatory logic electric circuit and the timing circuit. And with the emphasis laid on the consideration of representation requirements in the situations with and without feedback, the paper established the format suitable for both. Through the analysis of the requirements of truth table data characteristics during the logical synthesis and multiple sampling process, a method that makes the data pre-processed was proposed: the data should be sorted before sent to the logic synthesis, which could raise the logic synthesis processing speed greatly verified by the test.
Date of Conference: 25-28 July 2009