Test synthesis: an innovative approach to analog and system testability analysis using state dependent flow diagrams

The largest single effort associated with a testability analysis is the creation or modeling of tests. This paper presents a methodology, referred to as Test Synthesis, that automates the process of creating a set of tests that are suitable for performing a testability analysis and developing an initial test strategy. In the context of this paper, a test is defined as: "The acquisition or definition of data that leads to the detection of one or more faults". Test Synthesis combines topological data with testability models to create a comprehensive set of tests with minimal user input.