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A 10 \sim 15-bit 60-MS/s Floating-Point ADC With Digital Gain and Offset Calibration

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5 Author(s)
Yun-Shiang Shu ; Univ. of California at San Diego, La Jolla, CA, USA ; MoonJung Kyung ; Wei-Ming Lee ; Bang-Sup Song
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Floating-point analog-to-digital converter (FADC) utilizes an up-front variable-gain amplifier (VGA) to enhance its low-level resolution. Although it is a single-path system, varying gain by switching circuit elements in and out modulates the gain and offset as in the multi-path time-interleaved ADC. For high-speed operation at all gain settings, a constant-bandwidth switched-capacitor VGA is implemented with variable-bandwidth opamps, and its gain and offset are digitally calibrated in background using signal-dependent pseudo-random noise (PN) dithering and chopping techniques. A three-stage VGA adjusts its gain instantly from times 1 to times 32 depending on the sampled input level, and improves the INL of a 10-bit ADC from 24 to 0.9 least significant bits (LSBs) at a 15-bit level for the low-level input. The resulting 10 ~ 15-bit 60-MS/s ADC needs no input sample-and-hold (S/H) stage, and achieves a system noise of -80 dBFS with a gain set to times32. A prototype chip in 0.18-mum CMOS occupies an active area of 3.0times2.0 mm2, and consumes 300 mW at 1.8 V including digital calibration logic.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:44 ,  Issue: 9 )