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An FIR-Embedded Noise Filtering Method for \Delta \Sigma Fractional-N PLL Clock Generators

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4 Author(s)
Xueyi Yu ; Dept. of Electron. Eng., Tsinghua Univ., Beijing, China ; Yuanfeng Sun ; Woogeun Rhee ; Zhihua Wang

This paper describes a noise filtering method for ¿¿ fractional- N PLL clock generators to reduce out-of-band phase noise and improve short-term jitter performance. Use of a low-cost ring VCO mandates a wideband PLL design and complicates filtering out high-frequency quantization noise from the ¿¿ modulator. A hybrid finite impulse response (FIR) filtering technique based on a semidigital approach enables low-OSR ¿¿ modulation with robust quantization noise reduction despite circuit mismatch and nonlinearity. A prototype 1-GHz ¿¿ fractional-N PLL is implemented in 0.18 ¿m CMOS. Experimental results show that the proposed semidigital method effectively suppresses the out-of-band quantization noise, resulting in nearly 30% reduction in short-term jitter.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:44 ,  Issue: 9 )