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A Low Power, Scalable, DAC Architecture for Liquid Crystal Display Drivers

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2 Author(s)
Knausz, I. ; Nat. Semicond. Corp., Santa Clara, CA, USA ; Bowman, R.J.

The proliferation of portable electronic products such as cellular telephones and personal digital assistants has created a high demand for small format liquid crystal displays (LCD) with increasing bit resolution. The electronic drivers for these display applications must adhere to stringent power and area budgets. This paper describes a low-power, area efficient, scalable, digital-analog conversion (DAC) integrated circuit architecture optimized for driving small format LCDs. A 12 channel, 9-bit DAC driver based on this architecture, implemented in 0.5 mum CMOS technology and suitable for 1/4 VGA resolution displays, exhibited a 2 MSPS conversion rate, 252 muW power dissipation per channel using a 5 V supply, and a per DAC die area of 0.042 mm2. This performance sets a new standard for DAC display drivers in joules per bit areal density at less than 0.58 pJ per bit per mm2 .

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:44 ,  Issue: 9 )

Date of Publication:

Sept. 2009

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