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A new capacitor and opamp sharing technique that enables a very efficient low-power pipeline ADC design is proposed. A new method to cancel the effect of signal-dependent kick-back or memory effect in capacitors in the absence of a sample and hold is also presented. Fabricated in a 0.18 Â¿m CMOS process, the prototype 11-bit pipelined ADC occupies 2.2 mm2 of active die area and achieves 66.7 dB SFDR and 53.2 dB SNDR when a 1 MHz input signal is digitized at 80 MS/s. The SFDR and SNDR are unchanged for a 50 MHz input signal. The prototype ADC consumes 36 mW at 1.8 V supply, of which the analog portion consumes 24 mW.