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Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over {\rm GF}(2^{m}) Using Multiple Parity Prediction Schemes

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3 Author(s)
Chiou-Yng Lee ; Dept. of Comput. Inf. & Network Eng., Lunghwa Univ. of Sci. & Technol., Taoyuan, Taiwan ; Meher, P.K. ; Patra, J.C.

New bit-serial architectures with concurrent error detection capability are presented to detect erroneous outputs in bit-serial normal basis multipliers over GF(2m) using single and multiple-parity prediction schemes. It is shown that different types of normal basis multipliers could be realized by similar architectures. The proposed architectures can detect errors with nearly 100% probability.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:18 ,  Issue: 8 )