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A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration

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6 Author(s)
Aamir Zia ; Electr., Comput. & Syst. Eng. Dept., Rensselaer Polytech. Inst., Troy, NY, USA ; Philip Jacob ; Jin-Woo Kim ; Michael Chu
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Slow cache memory systems and low memory bandwidth present a major bottleneck in performance of modern microprocessors. 3-D integration of processor and memory subsystems provides a means to realize a wide data bus that could provide a high bandwidth and low latency on-chip cache. This paper presents a three-tier, 3-D 192-kB cache for a 3-D processor-memory stack. The chip is designed and fabricated in a 0.18 m fully depleted SOI CMOS process. An ultra wide data bus for connecting the 3-D cache with the microprocessor is implemented using dense vertical vias between the stacked wafers. The fabricated cache operates at 500 MHz and achieves up to 96 GB/s aggregate bandwidth at the output.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:18 ,  Issue: 6 )