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Parallel Interleavers Through Optimized Memory Address Remapping

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1 Author(s)
Jing-ling Yang ; Dept. of Electr. & Electron. Eng., Univ. of Hong Kong, Hong Kong, China

This work presents mathematical models and collision-free exchange rules for a parallel interleaver, using which it develops an optimized memory address remapping (OPMM) scheme that enables a classic interleaver to be exchanged for a parallel interleaver readily and efficiently. Both analytic and experimental results demonstrate that the rate of annealing achieved using the OPMM approach is much faster than that achieved using the traditional memory address remapping (MM) method.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:18 ,  Issue: 6 )

Date of Publication:

June 2010

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