By Topic

Trigated Poly-Si Nanowire SONOS Devices for Flat-Panel Applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Horng-Chih Lin ; Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu , Taiwan ; Ta-Wei Liu ; Hsing-Hui Hsu ; Chuan-Ding Lin
more authors

A new method is proposed and demonstrated to fabricate planar thin-film transistors and trigated nanowire (NW) devices simultaneously on the same panel. By using an oxide-nitride-oxide stack as the gate dielectric, the NW devices could also serve as nonvolatile Si-oxide-nitride-oxide-Si (SONOS) memory devices. Our results indicate that the combination of trigate and NW channels help to improve the device performance in terms of steppers subthreshold swing and reduced threshold voltage. Improvement in programming and erasing efficiency of the nonvolatile SONOS memory devices is also demonstrated with the trigated NW structure.

Published in:

IEEE Transactions on Nanotechnology  (Volume:9 ,  Issue: 3 )