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The block diagram of an idealized over-all error-correcting digital computer is presented. This computer has the property that during each unit time interval, it can correct the effects of a specific maxium number of transient-type component failures which might occur anywhere within it. Yet, all its combinational logic circuitry is only of the error-detecting type. The corresponding reduction in equipment that this design feature makes possible is achieved at the expense of the computer's having to sit idle during a large percentage of those time intervals in which component failures occur. In a sense, therefore, the computer utilizes a great deal of time-domain redundancy as well as equipment-domain redundancy. This paper discusses some of the design requirements that are involved in using this type of redundancy structure.