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A Reliability Model for Error Correcting Memory Systems

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2 Author(s)
Ayache, J.M. ; Laboratoire d''Automatique et d''Analyse des Systÿmes du CNRS; 7 Avenue du Colonel Roche; 31400 Toulouse, FRANCE. ; Diaz, M.

This paper evaluates the reliability of a memory system incorporating any sort of linear error-correcting code. If the failure hypothesis is too simple (viz, a failure affects the entire memory chip or only one memory bit) an evaluation of reliability can be wrong. The following considerations are thus important: 1. The failure model is based on the internal design of the memory chip. 2. The memory system hardware is accurately accounted for. The resulting model is very close to the hardware implementation and depends on six parameters. The model is very useful for easily comparing memory systems and for deriving tradeoffs among the implementation possibilities for the design of memory systems.

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Reliability, IEEE Transactions on  (Volume:R-28 ,  Issue: 4 )