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Recoded versus nonrecoded signed-digit number based digital parallel arithmetic: a case study

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1 Author(s)
Cherri, A.K. ; Dept. of Electr. & Comput. Eng., Kuwait Univ., Safat, Kuwait

Digital implementations for both the recoding and the addition steps for the signed-digit numbers require four or more logic levels (AND-OR) or (OR-AND) and at least 23 logic gates for each output bit. In this paper, a much simpler nonrecoding signed-digit adder is presented. Its hardware implementation requires much fewer logic gates and inputs lines than that for the recoded signed-digit one for the same number of logic levels

Published in:

Aerospace and Electronics Conference, 1995. NAECON 1995., Proceedings of the IEEE 1995 National  (Volume:2 )

Date of Conference:

22-26 May 1995

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