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Fault Tree Analysis Using Bit Manipulation

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4 Author(s)
Wheeler, Dean B. ; Bldg. 37, Rm. 578; Corporate Research & Development; General Electric Company; Schenectady, NY 12345 USA ; Hsuan, Jason S. ; Duersch, Ralph R. ; Roe, Glenn M.

This paper describes an efficient technique for computerized fault-tree analysis. The technique is based upon binary coding of events and bit manipulation for tree reduction, reducing both computation time and computer storage requirements. The operations include generation of minimal cut sets for trees containing arbitrary AND and OR logic, and determination of top event existence probability for s-independent minimal cut sets composed of s-independent basic events. By the use of an upward algorithm for tree reduction, information is available at each logic gate. The effectiveness in producing minimal cut sets and top event probability has been demonstrated through analysis of fault trees of various sizes. The current implementation accommodates trees containing AND and OR gates, including all logical redundancies.

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Reliability, IEEE Transactions on  (Volume:R-26 ,  Issue: 2 )