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Fast Carry Logic for Digital Computers

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3 Author(s)
Bruce Gilchrist ; Institute for Advanced Study, Princeton, N. J. ; J. H. Pomerene ; S. Y. Wong

Existing large scale binary computers typically must allow for the maximum full length carry time in each addition. It has been shown that average carry sequences are significantly shorter than this maximum, on the average only five stages for a 40 digit addition. A method is described to realize the implied 8 to 1 time saving by deriving an actual ``carry completion'' signal. Experimental results verify this saving.

Published in:

IRE Transactions on Electronic Computers  (Volume:EC-4 ,  Issue: 4 )