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Browse Journals & Magazines > Solid-State Circuits, IEEE Jo ...> Volume:25 Issue:2 Help

An ECL-compatible GaAs SCFL design method

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6 Author(s)
Shimizu, S. ; Toshiba Corp., Kawasaki, Japan ; Yoshihara, K. ; Terada, T. ; Ishida, K.
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A source-coupled FET logic (SCFL) circuit design method which provides compatibility with emitter-coupled logic (ECL) in terms of power supply voltage and logic level is described. The method considers device parameter variations (ΔVth, ΔR, and ΔK), and changes in the ambient temperature. A -0.2 V threshold voltage (Vth), a 0.9-V logic swing voltage (VSW), and a 0.35-V noise margin voltage (Vnm) were obtained to achieve compatibility with the ECL 10 K series power supply voltage of -5.2 V. A 5-Gb/s as well as a 3-Gb/s operational 4-b multiplexer and demultiplexer IC have been developed using this circuit design method

Published in:
Solid-State Circuits, IEEE Journal of  (Volume:25 ,  Issue: 2 )

Date of Publication: Apr 1990

Page(s):
539 - 545
ISSN :
0018-9200
INSPEC Accession Number:
3680857
Digital Object Identifier :
10.1109/4.52182
Product Type:
Journals & Magazines
Date of Current Version :
06 August 2002
Issue Date :
Apr 1990
Sponsored by :
IEEE Solid-State Circuits Society

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