By Topic

An ECL-compatible GaAs SCFL design method

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Shimizu, S. ; Toshiba Corp., Kawasaki, Japan ; Yoshihara, K. ; Terada, T. ; Ishida, K.
more authors

A source-coupled FET logic (SCFL) circuit design method which provides compatibility with emitter-coupled logic (ECL) in terms of power supply voltage and logic level is described. The method considers device parameter variations (ΔVth, ΔR, and ΔK), and changes in the ambient temperature. A -0.2 V threshold voltage (Vth), a 0.9-V logic swing voltage (VSW), and a 0.35-V noise margin voltage (Vnm) were obtained to achieve compatibility with the ECL 10 K series power supply voltage of -5.2 V. A 5-Gb/s as well as a 3-Gb/s operational 4-b multiplexer and demultiplexer IC have been developed using this circuit design method

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:25 ,  Issue: 2 )