An ECL-compatible GaAs SCFL design method

A source-coupled FET logic (SCFL) circuit design method which provides compatibility with emitter-coupled logic (ECL) in terms of power supply voltage and logic level is described. The method considers device parameter variations ( Delta V/sub th/, Delta R, and Delta K), and changes in the ambient temperature. A -0.2 V threshold voltage (V/sub th/), a 0.9-V logic swing voltage (V/sub SW/), and a 0.35-V noise margin voltage (V/sub nm/) were obtained to achieve compatibility with the ECL 10 K series power supply voltage of -5.2 V. A 5-Gb/s as well as a 3-Gb/s operational 4-b multiplexer and demultiplexer IC have been developed using this circuit design method.<
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