Referenced Items are not available for this document.
A high-speed 32×32-b parallel multiplier with an improved parallel structure using 0.8-μm CMOS triple-level-metal technology is discussed. A unit adder, a 4-2 compressor, enhances the parallelism of the multiplier array. A 25% reduction in the propagation delay time is achieved by using the compressor. The multiplier contains 27704 transistors with a 2.68-×2.71-mm2 die area. The multiplication time is 15 ns at 5 V with a power dissipation of 277 mW at 10-MHz operation. The triple-level-metal interconnection technology reduces the multiplier layout area. Compared with double-level-metal technology, a 27% chip size reduction is achieved
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:25
,
Issue:
2
)
Date of Publication: Apr 1990
- Page(s):
- 494 - 497
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 3680853
- Digital Object Identifier :
- 10.1109/4.52175
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Apr 1990
- Sponsored by :
- IEEE Solid-State Circuits Society
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