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A 16-b 160-kHz CMOS A/D converter using sigma-delta modulation

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6 Author(s)
Rebeschini, M. ; Motorola Inc., Schaumburg, IL, USA ; van Bavel, N.R. ; Rakers, P. ; Greene, R.
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The design and measured performance of a third-order sigma-delta analog-to-digital (A/D) converter sampling at 10.24 MHz that achieves a 91-dB signal-to-noise-plus-distortion ratio (RMS/RMS) with a 160-kHz output rate are discussed. The converter consists of three cascaded first-order sigma-delta modulators and a fourth-order comb decimation filter. A special autozeroed integrator having low pole error is required to achieve the 10.24-MHz sampling rate and high S/N. The modulator is implemented with fully differential switched-capacitor circuits and is manufactured using a 1.5-μm double-metal double-poly CMOS process

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:25 ,  Issue: 2 )

Date of Publication:

Apr 1990

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