Notification:
We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

Improving parallel circuit simulation using high-level waveforms

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Wen, Y.-C. ; Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA ; Gallivan, K. ; Saleh, R.

Waveform relaxation (WR) has been shown to be an effective algorithm to simulate large digital circuits. In this paper, we explore parallel WR methods to further improve the performance. The parallel processing issues under investigation include partitioning, task granularity, scheduling and allocation. The difficulty of addressing these issues is that circuit simulation problems tend to have highly irregular computational structures. The use of high-level waveforms generated from logic or timing simulators is introduced as a way of improving speed. The speed improvements for circuit partitioning, window selection and task allocation using high-level information are presented

Published in:

Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on  (Volume:1 )

Date of Conference:

30 Apr-3 May 1995