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A multi-level parallel simulation approach to electron transport in nano-scale transistors

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2 Author(s)
Mathieu Luisier ; Network for Computational Nanotechnology, Purdue University, West Lafayette, IN 47907, USA ; Gerhard Klimeck

Physics-based simulation of electron transport in nanoelectronic devices requires the solution of thousands of highly complex equations to obtain the output characteristics of one single input voltage. The only way to obtain a complete set of bias points within a reasonable amount of time is the recourse to supercomputers offering several hundreds to thousands of cores. To profit from the rapidly increasing availability of such machines we have developed a state-of-the-art quantum mechanical transport simulator dedicated to nanodevices and working with four levels of parallelism. Using these four levels we demonstrate that an almost ideal scaling of the walltime up to 32768 processors with a parallel efficiency of 86% is reached in the simulation of realistically extended and gated field-effect transistors. Obtaining the current characteristics of these devices is reduced to some hundreds of seconds instead of days on a small cluster or months on a single CPU.

Published in:

2008 SC - International Conference for High Performance Computing, Networking, Storage and Analysis

Date of Conference:

15-21 Nov. 2008