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A four-processor building block for SIMD processor arrays

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3 Author(s)
Fisher, A.L. ; Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA ; Highnam, P.T. ; Rockoff, T.E.

A four-processor chip, for use in processor arrays for image computations, is described. The large degree of data parallelism available in image computations allows dense array implementations where all processors operate under the control of a single instruction stream. An instruction decoder shared by the four processors on the chip minimizes the pin count allocated for global control of the processors. The chip incorporates an interface to an external SRAM (static RAM) for memory expansion without glue chips. The full-custom 2-μm CMOS chip contains 56669 transistors and runs instructions at 10 MHz. Five hundred and twelve 16-b processors and 4 Mbyte of distributed external memory fit on two industry standard cards to yield 5-billion instructions per second peak throughout. As image I/O can overlap perfectly with pixel computation, an array containing 128 of these chips can provide more than 600 16-b operations per pixel on 512×512 images at 30 Hz

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:25 ,  Issue: 2 )