By Topic

Parallelization resources of image processing algorithms and their mapping on a programmable parallel videosignal processor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Pirsch, P. ; Lab. for Informationstechnologie, Hannover Univ., Germany ; Kneip, J. ; Ronner, K.

For the design of a highly parallel programmable video signal processor, the parallelization resources and characteristic properties of image processing algorithms have been analyzed. Basing on the resulting algorithmic requirements, an architecture for a reduced instruction set processor with parallel data paths, called HiPAR-DSP, has been deduced. The processor consists of 4 or 16 parallel data paths with local data caches, coupled by a shared memory with matrix type data access. Control, memory and arithmetic architecture of the processor are properly balanced and adapted to the control flow and data access patterns of algorithms, resulting in a remarkable high sustained processing power for a broad spectrum of image processing algorithms

Published in:

Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on  (Volume:1 )

Date of Conference:

30 Apr-3 May 1995