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Synthesis and Analysis of a Cost Effective, Ultrareliable, High Speed, Semiconductor Memory System

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2 Author(s)
E. W. Husband ; School of Sciences and Technologies//University of Houston at Clear Lake City//Houston, Texas 77058 USA. ; S. A. Szygenda

This paper provides a detailed synthesis and analysis of a cost effective, ultrareliable, high speed, semiconductor memory system. The memory system has the capability of detecting and correcting over 99% of all single faults. The memory cycle time of 250 ns is not compromised unless a fault is encountered. The increase in circuitry for the fault-tolerent system, over the simplex system, is less than 20%. These results have been achieved through the use of special coding implementations, virtual codes, and selective redundance.

Published in:

IEEE Transactions on Reliability  (Volume:R-25 ,  Issue: 3 )