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This paper provides a detailed synthesis and analysis of a cost effective, ultrareliable, high speed, semiconductor memory system. The memory system has the capability of detecting and correcting over 99% of all single faults. The memory cycle time of 250 ns is not compromised unless a fault is encountered. The increase in circuitry for the fault-tolerent system, over the simplex system, is less than 20%. These results have been achieved through the use of special coding implementations, virtual codes, and selective redundance.