Referenced Items are not available for this document.
A low-power high-speed architecture for Σ-Δ modulators is proposed. Results are presented for a first-order Σ-Δ modulator constructed using a low-power fully-differential current-mode continuous-time integrator with a sampling frequency of 128 MHz. Deleterious effects due to glitches associated with the feedback D/A converter are circumvented through simple modifications of the system-level timing. The results are in good agreement with the theoretical limits: for an oversampling ratio of 128, behavioral simulations predict a maximum dynamic range of 56.9 dB for an input signal amplitude of -3 dB. Power dissipation for the first-order Σ-Δ modulator is 1 mW in a 1.2 μm CMOS process with a 3.3 V power supply
Published in:
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
(Volume:1
)
Date of Conference: 30 Apr-3 May 1995
- Page(s):
- 183 - 186 vol.1
- Meeting Date :
- 28 Apr 1995-03 May 1995
- Print ISBN:
- 0-7803-2570-2
- INSPEC Accession Number:
- 5086452
- Conference Location :
- Seattle, WA
- Digital Object Identifier :
- 10.1109/ISCAS.1995.521481
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