By Topic

Low-power high-speed continuous-time Σ-Δ modulators

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Mittal, R. ; Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA ; Allstot, D.J.

A low-power high-speed architecture for Σ-Δ modulators is proposed. Results are presented for a first-order Σ-Δ modulator constructed using a low-power fully-differential current-mode continuous-time integrator with a sampling frequency of 128 MHz. Deleterious effects due to glitches associated with the feedback D/A converter are circumvented through simple modifications of the system-level timing. The results are in good agreement with the theoretical limits: for an oversampling ratio of 128, behavioral simulations predict a maximum dynamic range of 56.9 dB for an input signal amplitude of -3 dB. Power dissipation for the first-order Σ-Δ modulator is 1 mW in a 1.2 μm CMOS process with a 3.3 V power supply

Published in:

Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on  (Volume:1 )

Date of Conference:

30 Apr-3 May 1995