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Floorplan area optimization using network analogous approach

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2 Author(s)
Kai Wang ; Dept. of Electr. Eng. & Comput. Sci., Illinois Univ., Chicago, IL, USA ; Chen, Wai-Kai

In this paper, we propose a new approach to solve a general floorplan area optimization problem. By using the analogy between a floorplan and a resistive network, we have shown that a class of zero wasted area floorplan can be achieved under the shape constraint of continuous aspect ratio. However, in many practical designs, each module may have constraints on its dimensions such as minimum length or width. In this paper, we define the floorplan area minimization problem under the constrained aspect ratio and give necessary conditions for the realization of zero wasted area floorplan under the shape constraints. A set of optimization methods is developed to minimize the wasted area if no zero wasted area floorplan is achievable. Examples are given to demonstrate the approach

Published in:

Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on  (Volume:1 )

Date of Conference:

30 Apr-3 May 1995