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Solid state modulators are increasingly being used in pulsed power applications. In these applications IGBT modules must often be connected in parallel due to their limited power capacity. In a previous paper, we introduced a control method for balancing the currents in the IGBTs. In this paper, we investigate techniques to minimize the modules' rise and fall times, which can positively impact the modulator's output pulse parameters, which in turn must meet the application's specifications. Further, a reduction in rise and fall times lowers switching losses and thus increases the modulator's efficiency. To reduce the voltage rise time of the pulse without increasing the maximal over-voltage of the parallel IGBTs we have investigated a double-stage gate driver with protection circuits to avoid over-voltages and over-currents. Additionally voltage edge detection has been implemented to improve current balancing. Our measurement results reveal the dependency of the rise-time and turnoff losses on the design parameters of the gate drive. We show that our design achieves a 62% reduction in the turn-off rise time, and a 32% reduction in the turn-off losses.