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Fault-tolerance and reconfigurability issues in massively parallel architectures

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3 Author(s)
Distante, F. ; Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy ; Sami, M.G. ; Stefanelli, R.

Fault tolerance is a basic requirement for many applications of massively parallel architectures; these, in turn, provide the opportunity to exploit regularity of the architecture to perform reconfiguration with a relatively simple interconnection structure and reduced number of spare elements. Interconnection complexity is taken as the guiding figure of merit. Reconfiguration approaches based on a stringent channel width limitation are presented. Performances are seen to be very good; furthermore, the solution can be extended to a comprehensive fault model, allowing the presence of faults in bus segments and switches as well as in PEs

Published in:

Computer Architectures for Machine Perception, 1995. Proceedings. CAMP '95

Date of Conference:

18-20 Sep 1995