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A scalable architecture for discrete wavelet transform

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2 Author(s)
S. B. Syed ; Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA ; M. A. Bayoumi

We present the design and prototyping of an efficient systolic architecture which performs both forward and inverse discrete wavelet transform. The proposed architecture consists of a linear array of processing elements, each of which has an adder and a multiplier and fixed number of I/O channels. The wavelet transform is computed by convolution and by mapping the computation on to a linear array of systolic processing elements. The design of the architecture has been shown to be simple, scalable and has the advantage of low I/O bandwidth. The number of processing elements is independent of the size of the input. The architecture has been prototyped using 2μm p-well CMOS technology and has been developed in the CADENCE Edge Design Framework environment

Published in:

Computer Architectures for Machine Perception, 1995. Proceedings. CAMP '95

Date of Conference:

18-20 Sep 1995