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Reliability-Enhancement and Self-Repair Schemes for SRAMs With Static and Dynamic Faults

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3 Author(s)
Jin-Fu Li ; Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan ; Tsu-Wei Tseng ; Chih-Sheng Hou

This paper proposes a simple method for enhancing the reliability of static random access memories (SRAMs) with hard-to-detect resistive-open defects. The method prevents a SRAM from executing successive multiple read operations on the same position, such that the hard-to-detect defects cannot manifest as functional faults. This can prolong the lifetime of the SRAM with latent hard-to-detect defects. Experimental results show that the proposed reliability-enhancement circuit (REC) can effectively improve the reliability of the SRAMs without incurring delay penalty and with 0.07% additional area cost for an 8192 × 64-bit SRAM. By integrating the REC with the SRAM, a BISR scheme is proposed to boost 6%-10% increment of repair rate compared with the BISR without the REC. Also, the area cost of the BISR is low-only about 2% for an 8192 × 64-bit SRAM.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:18 ,  Issue: 9 )