Referenced Items are not available for this document.
High-level synthesis facilitates the use of formal verification methodologies that check the equivalence of the generated RTL model against the original source specification. The article provides an overview of sequential equivalence checking techniques, its challenges, and successes in real-world designs.
Published in:
Design & Test of Computers, IEEE
(Volume:26
,
Issue:
4
)
Date of Publication: July-Aug. 2009
- Page(s):
- 88 - 95
- ISSN :
- 0740-7475
- INSPEC Accession Number:
- 10840405
- Digital Object Identifier :
- 10.1109/MDT.2009.79
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 21 August 2009
- Issue Date :
- July-Aug. 2009
- Sponsored by :
- IEEE Council on Electronic Design and Automation
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