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Statistical High-Level Synthesis under Process Variability

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2 Author(s)
Yuan Xie ; Pennsylvania State Univ., PA, USA ; Yibo Chen

CMOS process variability is a major challenge in deep-submicron SoC designs. The variations in transistor parameters are complicating both timing and power consumption prediction. This article surveys recent progress in the statistical high-level synthesis area.

Published in:

Design & Test of Computers, IEEE  (Volume:26 ,  Issue: 4 )