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An efficient hardware architecture is presented for computing convolutions and correlations with two or more dimensions. This is derived from combining a class of polynomial transforms with currently available VLSI convolution devices. The proposed method is particularly suitable for computing high order convolutions with little or no arithmetic quantisation errors.
Published in:
Electronics Letters
(Volume:26
,
Issue:
12
)
Date of Publication: 7 June 1990
- Page(s):
- 801 - 802
- ISSN :
- 0013-5194
- INSPEC Accession Number:
- 3680068
- Digital Object Identifier :
- 10.1049/el:19900523
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- 7 June 1990
- Sponsored by :
- Institution of Engineering and Technology
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