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Exploiting parallel microprocessor microarchitectures with a compiler code generator

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2 Author(s)
Hwu, W.-m.W. ; Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA ; Chang, P.P.

Several experiments using a versatile optimizing compiler to evaluate the benefit of four forms of microarchitectural parallelisms (multiple microoperations issued per cycle, multiple result-distribution buses, multiple execution units, and pipelined execution units) are described. The first 14 Livermore loops and 10 of the linpack subroutines are used as the preliminary benchmarks. The compiler generates optimized code for different microarchitecture configurations. It is shown how the compiler can help to derive a balanced design for high performance. For each given set of technology constraints, these experiments can be used to derive a cost-effective microarchitecture to execute each given set of workload programs at high speed

Published in:

Computer Architecture, 1988. Conference Proceedings. 15th Annual International Symposium on

Date of Conference:

30 May-2 Jun 1988