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Impact of the reduction of the gate to drain capacitance on low voltage operated CMOS devices

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5 Author(s)
Yamashita, K. ; Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka, Japan ; Nakaoka, H. ; Kurimoto, K. ; Umimoto, H.
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The effect of the gate to drain capacitance on low voltage operated CMOS devices is investigated. It is found that the Miller and feed-forward effects are enhanced with the reduction of the supply voltage. The reduction of the gate overlap capacitance as well as the threshold voltage and junction capacitance is a key issue to achieve high speed circuit operation at low supply voltage. We propose a low power, high speed T-gate CMOS device with dual gate structure using an amorphous-Si/poly-Si layer. A new process scheme is proposed to prevent boron penetration and to fabricate the T-gate structure effectively. It is found that the new T-gate CMOS with dual gate structure reduces the gate to drain overlap capacitance maintaining high current drivability at low power-supply voltage.

Published in:

VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on

Date of Conference:

6-8 June 1995