Skip to Main Content
A 0.25 /spl mu/m coded feature CMOS technology has been developed for high-performance, low-power ASIC applications. Critical process features include 248 nm DUV lithography on all levels, profiled twin tubs by high energy implantation (HEI), dual TiN/polysilicon gates with low resistance on minimum size lines, rapid thermal (RT) N/sub 2/O grown 5.5 nm gate dielectrics, and planarized multi-level interconnect. Transistors are demonstrated with symmetric thresholds and excellent short-channel characteristics down to channel lengths of 0.18 /spl mu/m. Fabricated circuits operate down to <1 V supplies, with <20 ps ring oscillator gate delays achieved for 0.2 /spl mu/m gate devices, a record for stepper-based lithography with conventional resist processing.
Date of Conference: 6-8 June 1995