Skip to Main Content
Silicon debug is becoming a key step in the implementation flow for the purpose of identifying and fixing design errors that have escaped pre-silicon verification. To address the lack of observability for the internal circuit nodes during silicon debug, embedded logic analysis enables real-time data acquisition from a limited number of internal signals. In this paper, we propose a novel architecture for embedded logic analysis that enables real-time lossless compression of debug data. To quantify the gain from using lossless compression in embedded logic analysis, we present a new compression-ratio metric that captures the trade-off between the area and the increase in the observation window. The proposed architecture is particularly suitable for in-field debugging on application boards, which have asynchronous events that inhibit the deterministic replay of debug experiments.