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Data Management: The Spirit to Pursuit Peak Performance on Many-Core Processor

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5 Author(s)
Yongbin Zhou ; Key Lab. of Comput. Syst. & Archit., Chinese Acad. of Sci., Beijing, China ; Junchao Zhang ; Shuai Zhang ; Nan Yuan
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To date, most of many-core prototypes employ tiled topologies connected through on-chip networks. The throughput and latency of the on-chip networks usually become to the bottleneck to achieve peak performance especially for communication intensive applications. Most of studies are focus on on-chip networks only, such as routing algorithms or router micro-architecture, to improve the above metrics. The salient aspect of our approach is that we provide a data management framework to implement high efficient on-chip traffic based on overall many-core system. The major contributions of this paper include that: (1) providing a novel tiled many-core architecture which supports software controlled on-chip data storage and movement management; (2) identifying that the asynchronous bulk data transfer mechanism is an effective method to tolerant the latency of 2-D mesh on-chip networks. At last, we evaluate the 1-D FFT algorithm on the framework and the performance achieves 47.6 Gflops with 24.8% computation efficiency.

Published in:

Parallel and Distributed Processing with Applications, 2009 IEEE International Symposium on

Date of Conference:

10-12 Aug. 2009

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