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10 gbit/s 0.0065 mm2 6 mw analogue adaptive equaliser utilising negative capacitance

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4 Author(s)
Lee, D. ; Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea ; Han, J. ; Han, G. ; Park, S.M.

An area- and power-efficient analogue adaptive equaliser (AEQ) is realised in a 0.13 m CMOS technology. The negative capacitance circuits are exploited at the equalisation filter to achieve wider bandwidth and larger high-frequency boosting, instead of using passive inductors that lead to a large chip area. Measured results demonstrate the data rate of 10 Gbit/s for 20 and 34 inch FR4 traces as channels, while dissipating only 6 mW from a single 1.2 V supply. The chip core occupies an extremely small area of 50 times 130 m2. To the best of the authors' knowledge, this chip achieves the lowest power consumption and the smallest chip area among the recently reported AEQs.

Published in:

Electronics Letters  (Volume:45 ,  Issue: 17 )

Date of Publication:

Aug. 13 2009

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