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The reconfigurable arithmetic processor

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2 Author(s)
S. Fiske ; Lab. for Comput. Sci., MIT, Cambridge, MA, USA ; W. J. Dally

The reconfigurable arithmetic processor (RAP), an arithmetic processing node for a message-passing, MIMD (multiple-input, multiple-data-stream) concurrent computer, is described. It incorporates on one chip several serial, 64-bit floating-point arithmetic units connected by a switching network. By sequencing the switch through different patterns, the RAP chip calculates complete arithmetic formulas. By chaining together its arithmetic units, the RAP reduces the amount of off-chip data transfer. Simulations have shown that off-chip I/O can often be reduced to 30% or 40% of that required by a conventional arithmetic chip. A peak performance of 20 MFLOPS (million floating-point operations per second) with 800-Mb/s off-chip bandwidth in 2-μm CMOS process is predicted

Published in:

Computer Architecture, 1988. Conference Proceedings. 15th Annual International Symposium on

Date of Conference:

30 May-2 Jun 1988