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We developed a new LSI chip based on the bit-parallel block-parallel functional memory type parallel processor (BPBP FMPP) architecture. The chip includes 1024 bit (32 word/spl times/32 bit) memory storage cells on a 45 mm/sup 2/ die using a 1.2 /spl mu/m CMOS process, and achieves 5 MHz clock rate at the worst case simulation. The BPBP FMPP LSI has capabilities of addition in O(1) and multiplication in O(m), where m represents the number of bits. Such functionality enhances its applicability into vast fields, where numerical operations are required.
Date of Conference: 8-10 June 1995