By Topic

Realistic CNFET based SRAM cell design for better write stability

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Ebrahimi, B. ; Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran ; Afzali-Kusha, A.

In this paper, a comparison between CNFET and Si-MOSFET SRAM cells at 32 nm technology node are presented. The designs are based on predictive technology model (PTM) for the Si-MOSFET cell and CNFET Stanford model for the CNFET cell. For practical reasons, in the CNFET case, the substrate of the entire chip is considered to be one node. The effect of the voltage of this node on improving the overall characteristics of the CNFET cell is described. HSPICE simulation results show that CNFET has better performance compared to Si-MOSFET. Finally, the characteristics of the SRAM cell in the presence of fabrication imperfections of CNFET are studied. The write stability of CNFET SRAM is low because of the same current drive capability for both p- and n-CNFETs. For solving this problem, we weaken the pull up transistors by different channel length and CNT diameter with respect to n type transistors.

Published in:

Quality Electronic Design, 2009. ASQED 2009. 1st Asia Symposium on

Date of Conference:

15-16 July 2009