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A power efficient digitally programmable delay element for low power VLSI applications

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2 Author(s)
Sekedi Bomeh Kobenge ; Department of Electronic Engineering, Tsinghua University Beijing China ; Huazhong Yang

Digitally programmable delay elements (DPDE) are required to be monotonic and low power. In this paper, a low power digitally programmable delay element (DPDE) with monotonic delay characteristics is proposed. A dynamic current mirror together with a feedback technique enables a current-on-demand operation. To avoid direct currents in the output transistors, an extra inverter is introduced to independently control the NMOS of the output inverter. The static power is eliminated while dynamic power is made proportional to the delay with a maximum of 36 uW when the unit is operating at 450 MHz.

Published in:

Quality Electronic Design, 2009. ASQED 2009. 1st Asia Symposium on

Date of Conference:

15-16 July 2009