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A novel variation-aware STA methodology is proposed. And with 65 nm process, the impact of this methodology is estimated. Statistical STA has come into use in order to consider process variation. But methodologies to consider SI such as crosstalk and PI such as voltage drop are still under investigations. In the point of PI, process variations are considered definitely. With the power shut off circuit, it is important to recognize which part in the circuit, power routing, normal transistors, or switch transistors is most sensitive to performance. From this acknowledgement, it is necessary to control variation of most sensitive elements and develop validation flow to handle these phenomena. In this paper, process variation impact on the power shut off circuit is analyzed with circuit simulation. It is measured how the variation of transistors' gate lengths and the variation of power routing resistance affect performance. Considering this phenomena, variation-aware STA methodology of power shut off circuit is proposed. With this method, applied different factors to transistors' gate lengths and power routing resistance, the degree of performance variation margin can be reduced by 75% compared to previous method.