By Topic

Comparative analysis of process variation impact on flip-flops soft error rate

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Mostafa, H. ; Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada ; Anis, M. ; Elmasry, M.

Due to CMOS technology scaling, devices are getting smaller, faster, and operating at lower supply voltages. The reduced capacitances and power supply voltages and the increased chip density to perform more functionality result in increasing the soft errors and making them one of the essential design constraints at the same level as delay and power. Even though the impact of process variations on the performance and the power consumption has been investigated by many researchers, its impact on soft errors has not been paid enough attention. This impact is investigated in this paper for 65-nm CMOS technology. The soft error yield is defined in this paper similar to the timing yield and the power yield. This paper shows that the soft error yield of the sense-amplifier based flip flop (SA-FF) is very poor. Therefore, soft error mitigation techniques are required when using this flip-flop topology. The semi-dynamic flip-flop (SD-FF) exhibits the best soft error yield behavior with a very high performance at the expense of large power requirement. Finally, some design insights are proposed to guide flip-flops designers to select the best flip-flop topology that satisfies their specific circuit soft error rate constraints.

Published in:

Quality Electronic Design, 2009. ASQED 2009. 1st Asia Symposium on

Date of Conference:

15-16 July 2009