Skip to Main Content
A novel ultra-low power control mechanism is presented for Mega-pixels current-mediated CMOS imagers. Within the proposed technique, the operating read-out pixel and reset pixel are located in the same column, controlled by only 2-bit lines/pixel compared with 4-bit in previous reported design. The number of transistors for each pixel is reduced from the standard 6 transistors to 4 in the current design. Because the read-out and reset modes are separated into two phases in series for the proposed mechanism, only one reference current source is used, by which the power consumption can further be saved and also the chip area would be shrunk. Minimum wiring overhead is required in the proposed pixel as two control lines are removed. Furthermore, a programmable electronic shutter is adopted to adjust the integration time. The proposed design is simulated using TSMC 0.18 um technology, with more than 80% fill factor for a 17 times 17 um2 pixel dimension.